⚡ Computing
Hertz to FLOPS
Estimate a processor's floating-point throughput from clock speed, core count and FLOPs per cycle. Press Convert.
About the Hertz to FLOPS
A hertz is one cycle per second. A CPU running at 3.5 GHz executes 3.5 billion cycles per second per core, but the number of floating-point operations completed in each cycle depends on the instruction set and the width of the execution units. A scalar add is one FLOP; an AVX-512 FMA instruction can complete 32 single-precision FMAs per core per cycle, counting as 64 FLOPs.
Peak FLOPS is therefore clock × cores × FLOPs per cycle. Real workloads rarely reach peak because of memory bandwidth, dependencies and instruction mix. The efficiency field lets you apply a realistic fraction — 50–80% for dense matrix code, much lower for sparse or branch-heavy work.
How the calculation works
- Peak FLOPS = clock (Hz) × cores × FLOPs per cycle.
- GFLOPS = FLOPS ÷ 10⁹; TFLOPS = FLOPS ÷ 10¹².
- Effective FLOPS = peak × efficiency.
- FLOPs per cycle depends on instruction width and FMA support.
Reference values
| Instruction | FLOPs/cycle/core | Notes |
|---|---|---|
| Scalar add | 1 | One operation |
| Scalar FMA | 2 | Multiply + add |
| SSE FMA (4-wide) | 16 | 4 lanes × 2 ops × 2 |
| AVX2 FMA (8-wide) | 32 | 8 lanes × 2 ops × 2 |
| AVX-512 FMA (16-wide) | 64 | 16 lanes × 2 ops × 2 |
| Dual AVX-512 FMA | 128 | Two FMA units |
Worked example: a CPU and a GPU
A 3.5 GHz, 8-core CPU with 16 FLOPs per cycle per core has a peak of 3.5 × 10⁹ × 8 × 16 = 448 GFLOPS. At 70% efficiency, expect about 314 GFLOPS. A GPU with 10,496 cores at 1.5 GHz and 2 FLOPs per cycle has a peak of 31.5 TFLOPS—before sparsity or tensor cores are counted.
Those peaks are upper bounds. Memory bandwidth, cache misses and instruction dependencies usually keep real code well below them. Quote the efficiency assumption whenever you compare two chips, otherwise the comparison is just a clock-speed contest.